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80×86中断和异常机制

overview

interrupt and exception :OS/processor/present task trigger an event which need to be processed by the processor.
I/E is used to represent interrupt/exception in the following contents
more accurate definition:

  • An interrupt is an asynchronous event that is typically triggered by an I/O device.
  • An exception is a synchronous event that is generated when the processor detects one or more predefined conditions while executing an instruction. The IA-32 architecture specifies three classes of exceptions: faults,traps, and aborts.
current\ program\xrightarrow[]{I/E}I/E\ handler
  • I/E mechanism is transparent for OS/program
  • recovery of program will not loss its concurrency

I/E vector

vector:an identifier for a particular processor-defined I/E
processor take the vector as an index in IDT(Interrupt Descriptor Table) to locate the entry of a I/E handler.

range

0-255
0-31:processor-defined
32-255:software-defined,either software interrupts or maskable hardware interrupts.

Table



NOTES:

  1. IA-32 processors after the Intel386 processor do not generate this exception.
  2. This exception was introduced in the Intel486 processor.
  3. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
  4. This exception was introduced in the Pentium III processor.
  5. This exception can occur only on processors that support the 1-setting of the “EPT-violation #VE” VM-execution control.

I/E source

interrupt source

interrupt ensures re-execution of the interrupted program.
the return pointer points to the instruction after the one that caught an exception

external interrupt(hardware)

  • INTR received: maskable interrupt(vector 0-255)
    IF flag in EFLAGS can be set to mask such interrupts
  • NMI received: non-maskable interrupt(vector 2)

software-generated

instruction INT n generate interrupt from software(vector 0-255)

exception source

processor detect

  • Fault : can be corrected. Recover to the instruction that generate a exception.
  • Trap : can be corrected. Recover to the instruction after the one which causes a exception.(if a JUMP instruction, then the return pointer points to jump destination)
  • Abort : disallow program recovery. report serious mistake such as hardware error.

    software-generated

    INT 0, INT 3 and BOUND instruction.

NOTE:caution for INT n instruction when n is a 80×86 vector.

I/E priority

When multiple I/E occur at the edge of an instruction, the one with highest priority will be processed first.
The rest exception will be thrown and the the rest interrupts keep waiting.
Thrown exceptions occur again when the program recover.



NOTE:

  1. The Intel® 486 processor and earlier processors group nonmaskable and maskable interrupts in the same priority class

About IDT / IDTR

The interrupt descriptor table (IDT) associates each exception or interrupt vector with a gate descriptor for theprocedure or task used to service the associated exception or interrupt.
IDT and IDTR(interrupt Descriptor Table Register)has the following structure:

  • IDTR is used to locate IDT
  • The IDT may reside anywhere in the linear address space.
  • LIDT : load IDTR with CPL=0 only
  • SIDT : save IDTR with any CPL
  • processor uses 8*vector to locate gate for interrupt in IDT because each descriptor is 8B

IDT descriptor

The IDT may contain any of three kinds of gate descriptors:
• Task-gate descriptor
• Interrupt-gate descriptor
• Trap-gate descriptor

  • Interrupt-gate and Trap-gate only differ in the way the processor handles the IF flag. They have the following procedure call:

  • When an exception or interrupt handler is accessed through a task gate in the IDT, a task switch results.

Reference

Intel® 64 and IA-32 Architectures Software Developer’s Manual

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